Multilayer ceramic chip capacitors (MLCCs) have developed rapidly and are being used in more and more applications. However, one thing that is often overlooked in designs is that direct current (DC) bias behavior affects the capacitance of Class 2 ceramic capacitors. For apparently unexplained reasons, this can cause the capacitance to fall outside the tolerance range of the application and can cause technical problems. However, there are ways to deal with this situation.

Multilayer ceramic chip capacitors (MLCCs) are one of the most widely used ceramic capacitors today, mainly due to their optimization in terms of maximum nominal C value and lower ESR value (equivalent series resistance). However, this is accompanied by greater drift, especially with respect to DC voltage, temperature and time.

Class 2 ceramic capacitors have now reached such high capacitance values that this will repeatedly lead to miscalculation of their actual capacitance during operation. People often don't know how components behave in real applications and why they change so much when voltage is applied. An important electrical parameter related to this is DC bias.

DC bias effect

DC bias effects can best be demonstrated in the laboratory. TDK used a 3216X7R1μF capacitor with a nominal voltage of 25V for testing and connected it to an LCR meter. This shows 1µF at 0V. If 25V is applied, more than 40% of the capacitance loss compared to the nominal capacitance value can be detected.

The reason for this lies in the actual structure of ceramic capacitors: their dielectric material is obtained from barium titanate, a ferromagnetic material whose molecules are attached to the structure barium 2+, oxygen 2-, titanium 4+. In this case, titanium is in the middle. The molecular structure has a cubic crystal structure above the Curie temperature (approximately +125°C) and changes to a tetragonal crystal structure below the Curie temperature. This creates a polarity called a dipole, where one side of the axis is more positive and the other side is more negative.

In the absence of an applied DC voltage, there is no electric field and the dipoles are randomly arranged throughout the crystal structure (spontaneous polarization). At the same time, the dielectric constant is high, which also results in high capacitance. If a low DC voltage is now applied, the electric field affects some of the dipoles due to polarization. They begin to line up parallel to the electric field, thus reducing the capacitance.

If a higher DC voltage is applied, several dipoles align themselves parallel to the electric field and the capacitance continues to decrease. When nominal voltage is applied to a capacitor, the capacitance level may drop by as much as 50% or more from the nominal capacitance level.

The effect of DC bias on the capacitance of Class 2 ceramic capacitors is unavoidable, but there are ways to deal with it.

Improve circuit design

Comparing several DC bias curves for Class 2 capacitors shows several possibilities for reducing the impact in the application:

Using a capacitor with 1nF and a nominal voltage of 16 V, the capacitance was reduced by almost 9% at 10 V and 21% at 16 V. For some designs, this is already an unacceptable situation. Using the same capacitor with a nominal voltage of 25 V, the capacitance drops only 2% at 10V.

This is because the dielectric layer in ceramic capacitors is thicker at higher nominal voltages, and a thicker dielectric means the electric field is weaker and has less of an effect on the dipole.

At 10 V, the capacitance change of a 470 pF capacitor in the same package size is only 0.6%. If the design allowed two of these capacitors to be connected in parallel, this would be a possible solution to the DC bias effect since the lower capacitance value allows for a thicker dielectric layer.

Sometimes, capacitors with the same capacitance value are also available in larger packages, which also typically have thicker dielectric layers and therefore better DC bias behavior.

Practical example: DC bias is not considered

A practical example to illustrate what happens if DC bias is not considered in the application: A customer uses a 08054.7 μF X5R multilayer ceramic capacitor at 25 V, with a nominal tolerance of 10% and a measurement parameter of 1 1 kHz at V eff . Customers complained that the components were defective because their C-value was only around 1 μF at 14.5V instead of around 1.5 μF like the "gold" samples. This results in a ripple signal at 15 V, which causes undervoltage of the IPM driver supply and poor commutation of the MOSFET, ultimately causing overcurrent in the motor windings.

The results show that capacitor manufacturers use two different raw material mixtures to maintain supply voltage reliability. At 14.5 V, one mixture showed values around 1µF and the other around 1.5µF. In other words, both fit the feature data. Where customers argue is using components with higher values for bias testing without examining the reasons for the differences, or considering the corresponding general diagrams. The threshold in the application is approximately 1.25μF. Initially, the customer happens to receive components with lower DC bias, and when the customer eventually receives components with more pronounced DC bias characteristics, these components exhibit undesirable behavior of the circuit.

In conclusion:

This example shows that in shortage situations it is particularly important to understand and consider the actual requirements of each function in the application and the behavior of the MLCC. It must be noted: Which actual voltage is necessary? What temperatures need to be considered in practice? Where is the threshold for effective capacitance value? When in doubt, developers should seek the advice of the capacitor manufacturer or distributor, especially if there are relatively significant deviations from the characteristic data and charts, as these are difficult to guarantee compared to specification data.

In this case, it is particularly recommended to use the DC bias curve of the capacitor to pre-check whether the capacitor is acceptable for the actual operating voltage. If this is not the case, there are three ways to minimize capacitive losses:

A. Connect two or more capacitors with lower capacitance in parallel

B. Choose a capacitor with a higher nominal voltage

C. Use capacitors with larger packages.

All three methods typically have thicker dielectric layers that help minimize capacitive losses due to DC bias. This avoids technical issues and provides developers with more options.